1. Technical Field
The present invention relates to semiconductor substrates, semiconductor devices, methods for manufacturing semiconductor substrates, and methods for manufacturing semiconductor devices, and it is particularly suitable for application to field effect transistors formed on a SOI (Silicon On Insulator) substrate.
2. Description of Related Art
The utilities of field effect transistors formed on a SOI substrate are attracting attention because of their readiness of element isolation, latch-up free characteristics, small source/drain junction capacitances and the like.
Also, for example, Japanese Laid-open Patent Application HEI 7-225410 (JP '410) describes a method of forming high breakdown voltage field effect transistors on a SOI substrate. Also, Japanese Laid-open Patent Application 2003-158091 (JP '091) describes a method of forming field effect transistors that are miniaturized on the other of submicron on a SOI substrate.
It is noted here that optimum film thicknesses of SOI layers differ for semiconductor elements of different usages. In other words, for a high breakdown voltage field effect transistor subjected to application of a high voltage load, its SOI layer needs to have a larger film thickness in order to secure the PN junction breakdown voltage, and the film thickness of the SOI layer amounts to the order of pm. For example, in the case of a high breakdown voltage field effect transistor having a drain breakdown voltage of about 100V, the film thickness of the SOI layer needs to be about several μm.
On the other hand, for a field effect transistor that is miniaturized on the order of submicron, its BOX layer needs to have a smaller film thickness in order to suppress punchthrough leakage and reduction of threshold values by short-channel effects, and thus the film thickness of the BOX layer becomes to be on the order of several hundred angstrom. For example, when the effective channel length becomes 0.1 μm or less, the film thickness of the SOI layer needs to be set to 50 nm or less.
In the meantime, accompanied by the advent of ubiquitous societies, the SOC (System On Chip) technology that enables mix-mounting of devices of various breakdown voltages and digital and analog devices on a single chip is attracting attention, for further promotion of miniaturization of information portable devices, reduction of power consumption, greater multiple functions, and greater capacities.
Also, Japanese Laid-open Patent Application 2002-299591 (JP '591) describes a method of forming semiconductor elements for different usages in active layers having thicknesses suitable for the respective usages by embedding dielectric films at different depths from a main surface of a semiconductor substrate, in order to realize the SOC on a SOI substrate.
However, according to the methods described in JP '410 and JP '091, the film thickness of the BOX layer is maintained at constant by the SOI substrate. For this reason, for forming semiconductor elements for different usages on a SOI substrate, the semiconductor elements need to be independently formed on different SOI substrates for the respective usages, which causes a problem that presents an obstruction to realization of the SOC.
Also, according to the method described in JP '591, in order to embed dielectric films at different depths from the main surface of the semiconductor substrate, oxygen ions are injected in a silicon substrate with different energies. For this reason, physical damages are generated in the silicon substrate, and the crystallinity and purity of the SOI layer deteriorate, thereby causing a problem in that, when semiconductor elements are formed in the SOI layer, their characteristics deteriorate due to PN junction leakages or the like.
Furthermore, according to the method described in JP '591, when mask deviations occur between the BOX layer and the element isolation layer, lacks or duplicates may occur in the BOX layer. For this reason, the element isolating separations among semiconductor elements become greater, and characteristics of elements near the element isolation regions deteriorate, which causes problems in that the degree of integration of semiconductor elements becomes lower, and the reliability of the semiconductor elements becomes deteriorated.